1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device in which an element isolation trench for isolating elements is formed, and relates to a method for manufacturing the same.
2. Description of the Related Art
Heretofore, an electrically erasable programmable read-only memory (EEPROM), which is capable of electrically rewriting data, has been known as a nonvolatile semiconductor memory. A MOS transistor, having a stacked gate structure formed by stacking a floating gate serving as a charge storage layer and a control gate, is generally used in a memory cell of the EEPROM.
One of the EEPROMs most suitable for increasing its capacity is a NAND type EEPROM disclosed in Japanese Patent Application Publication No. Hei 8-64700. The NAND type EEPROM includes a NAND cell unit in which multiple memory cells are connected to each other in series in such a manner that each adjacent two memory cells share a source/drain diffusion layer, and the multiple NAND cell units are arranged to form a NAND cell array. Each of the NAND cell units is provided with selection gate transistors arranged on both edges thereof, and is connected to a bit line and a common source line through the selection gate transistors.
The floating gates are separated for each memory cell, while the control gate is continuously patterned and formed as a word line (control gate line) shared by the memory cells arranged in one direction. The gate electrode of the selection gate transistor is also disposed in parallel with the word line as a selection gate line. A bit line disposed orthogonal to the word line is connected to the diffusion layer of the drain-side selection gate transistor of the NAND cell unit. A common source line is connected to the diffusion layer of the source-side selection gate transistor of the NAND cell unit.
Such a NAND cell unit has to drive a high voltage of, for example, 20V or more for writing to or erasing from a memory cell. However, in recent years, the miniaturization of the NAND cell unit has been advanced, so that the space between the word lines becomes narrower than the thickness of the gate oxide film of a high-voltage resistant transistor. Consequently, there arises a problem that voltage resistance between word lines is insufficient.